In SystemVerilog, you can use rand random function to select 3 random numbers. You can select these three numbers in a cycle and get a random number with rand()% 8, where% 8 is a modular operation to limit the range of random numbers from 0 to 7.

For example, you can use the following code to select three random numbers.

int data[8] = { 1，2，3，4，5，6，7，8 }；

int rand _ data[3]；

for(int I = 0； I<3; i++) {

rand _ data[I]= data[rand()% 8]；

}

//Send the data in the rand_data array.

In this code, we first define an array named data, which contains 8 numbers. Then, we define an array named rand_data to store three randomly selected numbers. Next, we use a loop to select three random numbers and store them in the rand_data array. Finally, we can use the data in the rand_data array to send it out.