order

Introduction to Chapter 1

1. 1 system chip is the inevitable development of microelectronics technology.

1.2 electronic design automation technology and hardware description language

1.2. 1 Overview of the development of electronic design automation technology

1.2.2 top. Down design method

1.2.3 hardware description language

Chapter 2 CMOS digital integrated circuits

2. 1 Introduction

2.2 Main production processes of integrated circuits

Wafer preparation

2.2.2 plate making

lithography

oxidate

deposition

corrode

spread

Conductor and resistance

2.3CMOS inverter and its layout

2.3. 1 MOS transistor and its layout

2.3.2CMOS inverter structure and its

field

2.4 Design Rules and Process Parameters

2.4. 1 Contents and functions of design rules

Geometric rules

Electrical rules

Characteristics of 2.5CMOS digital circuits

2.5. 1 standard logic level

Logical fan-out characteristic

2.5.3 Capacitive load and its influence

2.5.4 noise tolerance of CMOS circuits

2.6CMOS logic gate

2.6. 1 CMOS nor gate

2.6.2CMOS NAND gate

2.6.3 Multi-input CMOS logic gates

2.7NMOS transmission transistor and CMOS transmission gate

2.7. 1 NMOS transfer transistor

2.7.2CMOS transmission gate

utilize

Chapter 3 Hardware Description Language VHDL

3. 1 Introduction

3.2 Basic knowledge of VHDL

3.2. 1 VHDL program structure

HDL ... packages in the public repository

3.2.3 Lexical unit of VHDL

Data objects and types

Expressions and operators

3.3 VHDL structure description

3.3. 1 Description of structural behavior

RTL description of structure

Structural description of structure

3.4 substructure form of the structure

3.4. 1 process

3.4.2 Multi-process organization method of complex structure

3.4.3 yuan

subroutine

3.5 Sequential statements and concurrent statements

3.5. 1 sequential statements

3.5.2 Concurrent statement

3.6 signal and signal processing in VHDL

3.6. 1 signal drive source

Signal delay

3.6.3 Analog period and 8-delay of signal

Attribute function of signal

3.6.5 Signals with attribute function

3.7 other statements of VHDL

3.7. 1 Attribute Description and Definition Declaration

3. 7. 2 Asset statement

text

3.8 multivalued logic

3.8. 1 three-state numerical model

Multi-valued logic

3.9 Component instantiation

3.9. 1 Design common components

Construction package

Call of component

3. 10 configuration

3. 10. 1 default configuration

3. 10.2 Configuration of components

3. Configuration of10.3 block

3. Configuration of10.4 structure

utilize

The fourth chapter is the design of basic digital logic unit.

4. 1 combinational logic circuit design

4. 1. 1f] circuit

4. 1.2 tri-state buffer and bus buffer

4. 1.3 encoder, decoder and selector

4. Design of1.4 arithmetic unit

4. 1.5 ALU

4.2 sequential logic circuit design

4.2. 1 trigger

latch

register

4.2.4 Counter

4.3 memory

4.3. 1 Overview

Read-Only Memory

Random access memory

4.3.4 First in and then out of the stack

4.4 finite state machine

utilize

The fifth chapter is the hierarchical structure design of digital system.

5. 1 hardware algorithm model

5. Algorithm model of1.1FIFO stack.

5. 1.2 Algorithm of Booth One-bit Complement Multiplier

model

5.2 Division of Chip System

5.2. 1 parallel interface 8255

5.2.2 Structure of Booth's two's complement multiplier

design

5.3 Representation of Interconnection between Systems

5.4 System Simulation and Testing

5.4. 1 Overview

5.4.2 Simulation program design method

5. 4. 3 exlo establishes test procedures.

utilize

Chapter 6 SOC architecture

6. Structure of1SOC

6. 1. 1 Introduction

6. Hardware structure of1.2 SOC

6. 1.3 embedded software

6.2 embedded reduced instruction set processor in SOC

6.2. 1 Overview

Definition and characteristics of RISC

6.2.3 Instruction characteristics of RISC

6. 2. 4 RISC parallel processing technology

6.2.5 RISC/DSF structure

6. 2. 6 RISC kernel design

6.3 Architecture of Embedded Processor ARM

6.3. 1 Overview

ARM7 series processors

ARM9 series processors

6.3.4ARM9E series processors

6.3.5ARMl0 series processors

ARMll series processors

6.4 architecture of embedded processor MIPS324Kc

6.4. 1 Overview

6. 4. 2 IPS 324 KC embedded processor

6.5 interconnection mechanism of SOC

6.5. 1 Overview

6. 5. 2 MBA bus

Core connection bus

Bus and coach

6. 5. 5 CP bus

Virtual component interface

6.6 Embedded System Chip with ARM Core

for instance

6.6. 1LPC 2 100 series high-performance microcontroller

6.6.2a1191sam7x series high-performance microcontroller.

6.6.3AT9 1RM9200 High Performance Microcontroller

6.7 Embedded Real-time Operating System

6.7. 1 real-time operating system

6.7.2 Overview of Embedded Real-time Operating System

6.7.3 Real-time Multi-task Scheduling

Signal and semaphore

utilize

Chapter 7 Programmable Logic Devices

7. 1 overview

7. 1. 1 Development of Programmable Logic Devices

7. 1.2 user reconfigures circuit and programmable ASIC.

circuit

7. 1.3 classification of programmable logic devices

7.2 Programming elements of programmable logic devices

7.2. 1 fuse switch

Anti-fuse switch

7.2.3 floating gate programming technology

7.3 Circuit structure of PAL and GAL equipment

7.3. 1 PLD circuit representation method

7.3.2 Basic circuit structure of PLD

7.3.3 Circuit structure of PAL equipment

7.3.4 generic array logic GAL

7.4ispLSI series CPLD

7.4. 1 Overview

7.4.2 Structural Features of ISP LSI1000 Series CPLD

7.4.3 Test and programming characteristics of ISP LSI CPLD

7. 4. 4 ISP LSI 2000 series CPLD structure

IspLSI3000 series CPLD

7.4.6 The structure of ISP LSI 5000 V series CPLD and

principle of operation

7.4.7 Structure of ISP LSL8000/V Series CPLD

And working principle.

7.5 Field Programmable Gate Array

7.5. 1 Overview

7.5.2 structure and construction of xc4000 series FPGA

principle of operation

7. 5. 3 partial series FPGA

7.6 System Design and Implementation Based on High Density Programmable Logic Device

Overview of design and implementation

Selection of equipment

7.6.3 Design Process of HD PLD

utilize

Chapter 8 Programmable System Chip

8. 1 Overview of Programmable System Chip

8.2 virtex-Ⅱ series FPGA structure and

perform

8.2. 1 Overview

8.2.2 Overview of Virtex-II series FPGA

structure

8.2.3 Configurability of Virtex-II series FPGA

logical module

8. 2. 4 18 kilobit optional RAM module

Embedded multiplier

8.2.6 Global clock multiplexing buffer

8.2.7 Digital Clock Manager

Input and output module

8.2.9 Active Interconnection Technology

8.3 embedded RISC processor soft core MicroBlaze

8.3. 1 embedded micro-Blaze human-computer processor soft core

general situation

8.3.2 MicroBlaze of embedded processor soft core

structure

8.3.3 MicroBlaze of embedded processor soft core

Interface signal

8.4 virtex-ii pro series programmable system on chip

chip

8.4. 1 virtex-ii pro SOPC series overview

8.4.2 Embedded PowerPc405 processor core

8.4.3 Speed bidirectional serial transmitter

utilize

Chapter 9 ASIC design

9. 1 Introduction

9.2 Design of Gate Array and Gate Array

9.2. 1 gate array design

Entrance array

9.2.3 Gate Array and Design Process of Gate Array

9.3 Standard Unit Design

9.4 Design check

9.4. 1 Design Rule Inspection

Inspection of electrical rules

9.4.3 consistency check between layout and circuit diagram

Simulation after 9.5

utilize

Chapter 10 testable structural design

10. 1 LSI testable design

meaning

10.2 testability basis

10.2. 1 failure mode

10.2.2 testability analysis

10.2.3 test vector generation

LO.2.4 fault simulation

Testability structure design of 10.3 integrated circuit

1 special test design

10.3.2 scan test design

10.3.3 Built-in self-checking technology

10.3.4 system-level testing technology-boundary scanning

Testing technology

utilize

appendix

Appendix AVHDL standard package collection file

Appendix BIP core list

refer to