Reconfigurable Computing (CGRA) architecture is essentially a spatial parallel computing model, which organizes computing resources with different granularity and different functions through spatial hardware structure, adjusts hardware functions through hardware configuration during operation, and interconnects hardware resources and configured functions according to the characteristics of data flow to form a relatively fixed computing path, and performs data-driven computing in a way close to "dedicated circuit" (as shown in figure 1).

When the algorithm and application are converted, the hardware is reconfigured into different computing paths through reconfiguration (as shown in Figure 2). The biggest advantage of CGRA lies in two aspects: one is that there is no delay and energy consumption in fetching and decoding operations in the traditional instruction-driven computing architecture, and the other is that it is executed in a way close to "special circuit" in the calculation process.

Therefore, the reconfigurable computing architecture chip has the characteristics of high performance and low power consumption.